rai o ra8835a dot matrix lcd controller specification version 1.0 february 7, 2007 ra i o technology inc. ?copyright raio technology inc. 2006, 2007 rai o technology inc. 1/6 www.raio.com.tw
preliminary version 1.0 dot matrix lcd controller ra8835a rai o technology inc. 2/6 www.raio.com.tw 1. overview the ra8835a is a controller ic that can display text and graphics on lcd panel. it can display layered text and graphics, scroll the display in any direction and partition t he display into multiple screens. it also stores text, character codes and bitmapped graphics data in external frame buffer memory. display controller functions include transferring data from the controlling microproc essor to the buffer memory, reading memory data, converting data to display pixels and generating timing signals for the buffer memory, lcd panel. the ra8835a has an internal character generator with 160, 5 x ?7 pixel characters in internal mask rom. the character generators support up to 64, 8 x ? 16 pixel characters in external character generator ram and up to 256, 8 x ?16 pixel characters in exter nal character generator rom. 2. features ? text, graphics and combined text/graphics display modes ? three overlapping screens in graphics mode ? up to 640 x ?256 pixel lcd panel display resolution ? programmable cursor control ? smooth horizontal and vertical scrolling of all or part of the display ? 1/2-duty to 1/256-duty lcd drive ? up to 640 x ?256 pixel lcd panel display resolution memory ? 160, 5 x ?7 pixel characters in internal mask- programmed character generator rom ? up to 64, 8 x 16 pixel characters in external character generator ram ? up to 256, 8 x 16 pixel characters in external character generator rom ? 6800 and 8080 family microprocessor interfaces ? low power consumption?3.5 ma operating current (v dd = 3.5v), 0.05 a standby current ? package: ra8835ap3n: qfp-60 pin (lead free) RA8835AP4N: tqfp-60 pin (lead free) ? power: 2.7 to 5.5 v 3. block diagram display ram i/f 256byte cgrom d [7:0], c s , r d , w r x d x g y d is , l p , w f , x s c l , a 0, r e s , s e l 1, s e l 2 y d , y s c l , x d [3:0] registers block timing generator mcu i/f cursor c o n tro ller x?tal osc data latch system configure v a[15:0], vd [7:0], vce, vrd, vwr test
preliminary version 1.0 dot matrix lcd controller ra8835a rai o technology inc. 3/6 www.raio.com.tw 4. package raio ra8835ap3n tm 07xx xd cs a0 vdd d0 d1 d2 d3 d4 d5 d6 date code(year 2007) 6 10 15 20 35 30 29 25 50 45 40 60 1 5 va8 va9 va10 va11 va12 va13 nc va14 va15 vd0 vd1 vd2 xg sel1 sel2 wr rd nc nc res vrd vce vwr va0 va1 va2 va3 va4 va5 va6 va7 d7 xd3 xd2 xd1 xd0 xecl xscl gnd lp wf ydis yd yscl vd7 vd6 vd5 vd4 vd3 index figure 4-1: ra8835ap3n(qfp-60 pin) raio RA8835AP4N tm 07xx date code(year 2007) 1 15 30 16 46 60 vd4 vd5 vd6 vd7 yscl yd ydis wf lp gnd xscl secl xd0 xd1 xd2 va5 va4 va3 va2 va1 va0 vwr vce vrd res nc nc rd wr sel2 index vd3 vd2 vd1 vd0 va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 nc xd3 d7 d6 d5 d4 d3 d2 d1 d0 vdd a0 cs xd xg sel1 45 31 raio RA8835AP4N tm 07xx date code(year 2007) 1 15 30 16 46 60 vd4 vd5 vd6 vd7 yscl yd ydis wf lp gnd xscl secl xd0 xd1 xd2 vd4 vd5 vd6 vd7 yscl yd ydis wf lp gnd xscl secl xd0 xd1 xd2 va5 va4 va3 va2 va1 va0 vwr vce vrd res nc nc rd wr sel2 index vd3 vd2 vd1 vd0 va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 nc vd3 vd2 vd1 vd0 va15 va14 va13 va12 va11 va10 va9 va8 va7 va6 nc xd3 d7 d6 d5 d4 d3 d2 d1 d0 vdd a0 cs xd xg sel1 xd3 d7 d6 d5 d4 d3 d2 d1 d0 vdd a0 cs xd xg sel1 45 31 figure 4-2: RA8835AP4N (tqfp-60 pin) 5. pin descriptions 5.1.1. mcu interface pin name function d0 to d7 mcu data bus. tri-state input/output pins. connect these pins to an 8- or 16-bit microprocessor bus. sel1, sel2 mcu interface select. the ra8835a series supports both 8080 fa mily processors (such as the 8085 and z80?) and 6800 family processors (such as the 6802 and 6809). sel1 should be tied directly to vdd or vss to prevent noise. if noise does appear on sel1, decouple it to ground using a capacitor placed as close to the pin as possible. sel1 sel2* interface a0 rd wr cs 0 0 8080 family a0 rd wr cs 1 0 6800 family a0 e r/ w cs rd or e read control or enable. when the 8080 family interface is selected, this signal acts as the active-low read strobe. the ra8835a series output buffers are enabled when this signal is active. when the 6800 family interface is selected, this signal acts as the active-high enable clock. data is read from or written to the ra8835a series when this clock goes high.
preliminary version 1.0 dot matrix lcd controller ra8835a rai o technology inc. 4/6 www.raio.com.tw wr or r/ w write control or read/write control. when the 8080 family interface is selected, this signal acts as the active-low write strobe. the bus data is latched on the rising edge of this signal. when the 6800 family interface is selected, this signal acts as the read/write control signal. data is read from the ra8835a series if this signal is high, and written to the ra8835a series if it is low. cs chip select. this active-low input enables the ra8835a series. it is usually connected to the output of an address decoder device that maps the ra8835a series into the memory space of the controlling microprocessor. a0 command/data select. 8080 family interface: 6 800 family interface: a0 rd wr function 0 0 1 status flag read 1 0 1 display data and cursor address read 0 1 0 display data and parameter write 1 1 0 command write a0 r/ w e function 0 1 1 status flag read 1 1 1 display data and cursor address read 0 0 1 display data and parameter write 1 0 1 command write res hardware reset. this active-low input performs a hardware reset on the ra8835a series. it is an schmitt-trigger input for enhanced noise i mmunity; however, care should be taken to ensure that it is not triggered if the supply voltage is lowered. 5.1.2 display memory control the ra8835a series can directly access static ram and prom. the designer may use a mixture of these two types of memory to achieve an opt imum trade-off between low cost and low power consumption. pin name function va0 to va15 16-bit display memory address. when accessing character generator ram or rom, va0 to va3, reflect the lower 4 bits of the ra8835a row counter. vd0 to vd7 display memory data bus. 8-bit tri-state display memory data bus. these pins are enabled when vrd or vwr is low. vwr display memory write control. active-low display memory write control output. vrd display memory read control. active-low display memory read control output.
preliminary version 1.0 dot matrix lcd controller ra8835a vce display memory chip select. active-low static memory standby control signal. vce can be used with cs . 5.1.3 lcd drive signals in order to provide effective low-power drive fo r lcd matrixes, the ra8835a series can directly control both the x- and y-drivers using an enable chain. pin name function xd0 to xd3 data output for driver. 4-bit x-driver (column drive) data outputs. connect these outputs to the inputs of the x-driver chips. xscl latch clock. the falling edge of xscl latches the data on xd0 to xd3 into the input shift registers of the x-drivers. to conser ve power, this clock halts between lp and the start of the following display line (see section 6.3.7). xecl trigger clock for chain cascade. the falling edge of xecl triggers the enable chain cascade for the x-drivers. every 16th clock pulse is output to the next x-driver. lp latch pulse. lp latches the signal in the x-driver sh ift registers into the output data latches. lp is a falling-edge triggered signal, and pulses once every display line. connect lp to the y-driver shift clock on modules. wf ac drive output. the wf period is selected to be one of two values with system set command. yscl latch clock for yd. the falling edge of yscl latches the data on yd into the input shift registers of the y-drivers. yscl is not used with driv er ics which use lp as the y-driver shift clock. yd data pulse output for y drivers. it is active during the last line of each frame, and is shifted through the y drivers one by one (by yscl), to scan the display?s common connections. ydis power-down output signal. ydis is high while the display drive outputs are active. ydis goes low one or two frames after the sleep command is written to the ra8835a series. all y- driver outputs are forced to an intermediate level (de-selecting the display segments) to blank the display. in order to implement power-down operation in the lcd unit, the lcd power drive supplies must also be disabled when the display is disabled by ydis. 5.1.4. oscillator and power pin name function xg crystal connection for internal oscillator this pin can be driven by an external cl ock source that satisfies the timing specifications of the ext f0 signal (see section 7.3.6). xd crystal connection for internal oscillator leave this pin open when using an external clock source. vdd 2.7 to 5.5v supply. this may be the same supply as the controlling microprocessor. rai o technology inc. 5/6 www.raio.com.tw
preliminary version 1.0 dot matrix lcd controller ra o technology inc. 6/6 www.raio.com.tw ra8835a gnd ground test test pin. this is a test pins. no need for connection(nc). note: the peak supply current drawn by the ra8835a series may be up to ten times the average supply current. the power supply impedance must be kept as low as possible by ensuring that supply lines are sufficiently wide and by placing 0.47 f decoupling capacitors that have good high-frequency response near the device?s supply pins. 6. system application ra8835a mcu lcd panel sram lcd driver lcd driver i
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